Detect changes in std_logic vhdl -


i trying detect changes in input signals of selector. when find first input changed (either rising or falling edge), give index output. when try synthesize source code, error "unsupported clock statement". tried use "rising_edge" , "falling_edge", got same error. here code

library ieee; use ieee.std_logic_1164.all;  entity selector port ( x1:  in std_logic; x2:  in std_logic; x3:  in std_logic; x4:  in std_logic; x5:  in std_logic; x6:  in std_logic; o:       out std_logic_vector(2 downto 0) ); end selector;   architecture behave of selector begin process(x1,x2,x3,x4,x5,x6) begin     if (x1'event)             o <= "000";     elsif (x2'event)             o <= "001";     elsif (x3'event)             o <= "010";     elsif (x4'event)             o <= "011";     elsif (x5'event)             o <= "100";     elsif (x6'event)             o <= "101";     else             o <= "000";     end if; end process; end behave;

is there alternative solution that?

you need additional clock input make comparison between value of x1, x2, ... in current clock cycle , value in last clock cycle. if xes asynchronous clock have synchronize them first.

input synchronisation

to synchronize inputs clock, have sample each input 2 d flip-flops in serial. output of first flip-flop may harmed metastability problems described in more detail in these papers:

the connection between both flip-flops (for each input) must constrained rounting path between them short possible. implementation below show 2 flip-flops. more advanced implementation can found in sync_bits component of poc library 1 of authors.

comparison

once input synchronous clock, delay clock cylce. make last value, that, can compare current values last values detect signal change. frequency of input clock must faster frequency of change on 1 of x inputs:

  • to fast repsonse of edge-detection, and
  • to catch signal changes.

here possible implementation:

library ieee; use ieee.std_logic_1164.all;  entity selector     port (         clk : in std_logic;         x1:  in std_logic;         x2:  in std_logic;         x3:  in std_logic;         x4:  in std_logic;         x5:  in std_logic;         x6:  in std_logic;         o:   out std_logic_vector(2 downto 0)     ); end selector;  architecture behave of selector     signal x : std_logic_vector(6 downto 1); -- inputs in 1 vector     signal x_meta : std_logic_vector(6 downto 1); -- first  sampling stage     signal x_curr : std_logic_vector(6 downto 1); -- second sampling stage =                                                   -- current value     signal x_last : std_logic_vector(6 downto 1); -- last value of x_curr begin     -- concatenate inputs 1 vector shorter code below.     x <= x6 & x5 & x4 & x3 & x2 & x1;      -- synchronize external inputs clock. if x* inputs     -- synchronous 'clk' replace process with:     -- x_curr <= x;     sync: process(clk)     begin         if rising_edge(clk)             -- path betweeen these 2 flip-flops must constrained             -- short delay, that, wire in between ahort             -- possible.              x_meta <= x;             x_curr <= x_meta;         end if;     end process;      -- statement delays current value x_curr 1 clock cycle.     x_last <= x_curr when rising_edge(clk);      -- comparison , selector output.     process(x_curr, x_last)     begin         if    (x_curr(1) xor x_last(1)) = '1'             o <= "000";         elsif (x_curr(2) xor x_last(2)) = '1'             o <= "001";         elsif (x_curr(3) xor x_last(3)) = '1'             o <= "010";         elsif (x_curr(4) xor x_last(4)) = '1'             o <= "011";         elsif (x_curr(5) xor x_last(5)) = '1'             o <= "100";         elsif (x_curr(6) xor x_last(6)) = '1'             o <= "101";         else             o <= "000";         end if;     end process; end behave;

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