VHDL - WAIT ON <signal> statement -

i'm trying work through example of wait on statement. every time try compile code the compiler, quartus ii gives me following error message.

error (10533): vhdl wait statement error @ t1.vhd(23): wait statement must contain condition clause until keyword

the model architecture below. function not important reason why compiler asking until statement. examples have seen, internet , books show use such below:

architecture dflow of t1 signal middle   : std_logic; begin p1 : process begin         if clk = '1'             middle <= input;         end if;     wait on clk; end process p1; output <= middle; end architecture dflow; 

best regard d

i think basic problem here line

wait on clk; 

is waiting any type of event on clk. transition 'h' '1', example, or either rising or falling edge of clk. in either of these cases, there no real hardware in fpga can work in way. may seem obvious you looking rising edge, because of if clk = '1' line, not how synthesis tool seeing it.

by adding until, can narrow down particular event interested in, selecting can realised in fpga. examples:

wait on clk until clk = '1'; -- detect rising edge, ok (ish, see below) wait on clk until clk = '0'; -- detect falling edge, ok (^^) 

this method analogous clk'event , clk = '1' technique of edge detection. not recommended method, because can simulation mismatch reality due simulator responding transitions 'h' '1' (among other possibilities), hardware cannot do.

the recommended method of detecting edges rising_edge , falling_edge functions:

wait until falling_edge(clk); -- ok, no ambiguity here. 

finally, whole structure represented here looks pretty non-standard. common way write clocked process this:

process (clk) begin   if (rising_edge(clk))     --   end if; end process;