VHDL synchronization between different blocks -


i have tried hard search solutions on internet. failed thats why put here.

i trying design i2c block in fpga. receives data, mode information other blocks. after receiving, i2c export or read data environment devices.

my question is, when i2c communicating other blocks inside fpga, how i2c synchronize other blocks? mean how i2c know if data , mode received other blocks previous? or updated?

my current idea use pulse generated other blocks inform i2c "new data" coming. know if there other ways? differences between these methods?

thank much.

best regards

if read um10204 i2c-bus specification , user manual (pdf, 1.4 mb) might find i2c more complex might expect defined.

a reference design in vhdl might come in handy. try frank buss's i2c slave pca9555 example implementation (zip, 829kb). pca9555 (data sheet, pdf 529kb) shows read , write pulses 2 8 bit port devices i2c interface. interrupt used signal input port event cause master read device. i've used pca9555 family devices in manner sonet alarm stuff.

your 'pulse generated other blocks inform' sounds compatible. alternative might have either 2 i2c buses or otherwise both master , slave devices both on 1 or more design blocks. lattice semiconductor has reference master design (see i2c (inter-integrated circuit) bus master controller, zip file download 494kb, both vhdl , verilog, licensed lattice implementation only) might used teach own master design implementation, useful traffic generators verification.


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